1. Field of the Invention
The present invention relates to a semiconductor device for use in a logic integrated circuit, a semiconductor memory, or the like which is incorporated in an electronic computer, a main storage device thereof, an office-automation device, a personal computer, a game device, or the like, the semiconductor device having a structure capable of reading and writing data at high speed and suitable for high-density integration, and a method of manufacturing such a semiconductor device which has a potential barrier controllable by an external bias to generate an optimum potential barrier.
2. Description of the Prior Art
Recent years have been seeing a rapid progress in high-speed semiconductor devices and highly integrated semiconductor devices. Particularly, efforts that have heretofore been made to produce highly integrated semiconductor devices have resulted in a mass production of 16-Mbit memories, and have also revealed a 64-Mbit memory prototype.
However, conventional attempts to achieve a higher degree of integration for semiconductor devices have been encountering some problems. Specifically, simply reducing the size of the structure of a present semiconductor memory configuration of the MOS (metal oxide semiconductor) type or VMOS (V-groove metal oxide semiconductor) type would cause the number of electrons that contribute to the operation of the semiconductor memory to be reduced closely to a noise level, making it difficult to control the operation of the semiconductor memory. This drawback is serious with respect to 64-Gbit memories where the number of electrons involved in the memory operation is about 100 or less. The problem is not only limited to semiconductor memories, but also applies to semiconductor devices which are affected by the number of operating electrons.
To alleviate the above shortcomings, the inventor has already proposed a semiconductor memory composed of basic memory cells each comprising a static inductor transistor (SIT) (see IEEE Journal of solid-state circuits, vol. SC-13, No. 5, October 1978, p. 622, "High Speed and High Density Static Induction Transistor Memory").
SIT memories are classified by circuit operation into a two-terminal memory (ping-pong memory) and a three-terminal memory (purse memory). Semiconductor memories are basically brought under three categories, i.e., a serial memory or shift register, a random-access memory (RAM), and a read-only memory (ROM), by the manner in which they store in formation. The inventor has disclosed in the above publication that the semiconductor memories of the three types can be constructed of SITs.
The SIT memories can be integrated to a scale several times greater than presently available MOS or VMOS memories because the SIT memories can be arranged in a three-dimensional structure by embedding part of the memory in the semiconductor substrate. The SIT memories operate at very high speed owing to bulk conduction rather than surface conduction, and can be constructed for high storage capacity due to a low power requirement.
SIT ping-pong memories and purse memories have their characteristics of holding stored information depending on the intrinsic gate potential which is determined by the difference between the Fermi level in the vicinity of a MOS capacitor on a drain region which is a storage region and the potential of a source region. Therefore, as electrons are stored in an electron-storage-type memory, the potential of the memory increases and the intrinsic gate potential under goes a corresponding reduction, with the result that the leak current increases and the holding characteristics of the electron-storage-type memory are degraded. In order to improve the holding characteristics, a reverse gate bias may be applied in advance, which would require a high voltage to be applied upon reading and writing information.
When a charge is stored in an electron-depletion-type memory, the potential of the memory decreases and the intrinsic gate potential increases, thus improving the holding characteristics of the memory. However, the rate at which information can be read from and written in the electron-depletion-type memory is lower than that of the electron-storage-type memory.
In the SIT memories, since the surface storage electric capacitance is driven in principle by a static induction transistor, it is necessary to form p.sup.+ gate regions as lands in an n.sup.- channel region so as to cause pinchoff in the n.sup.- channel region. The SIT memories control the carrier transport between the storage region and the source region by controlling the intrinsic gate potential which is developed between an n.sup.+ drain region formed between the p.sup.+ gate regions and an n.sup.+ source region formed in a position that confronts the n.sup.+ drain region. Specifically, the carrier transport is controlled by a static induction effect caused by a voltage applied to the surface electrode in a gate-floating two-terminal SIT memory configuration, and by both a static induction effect caused by a voltage applied to the surface electrode and an intrinsic gate potential developed by an external gate voltage in a gate-floating three-terminal SIT memory configuration.
Therefore, the conventional SIT memories remain to be improved for high-speed and low-noise operation since the carrier transport that is carried out between the storage region and the source region under the intrinsic gate potential control is governed by the Boltzmann's formula.
Transistors, e.g., npn-type bipolar transistors (BPT), have a neutral region left in a junction barrier layer. FIG. 1 of the accompanying drawings shows the potential distribution of an npn-type bipolar transistor. In FIG. 1, no electric field is applied because a flat area is left in the potential of a barrier layer top region 1. Therefore, for storing a carrier such as electrons from a source region into a storage region and drawing the carrier from the storage region into the source region in writing and reading modes during operation of a semiconductor memory, the carrier has to be transferred by way of diffusion through the flat-potential region of the barrier layer, imposing a limitation on high-speed memory operation. The presence of the neutral region prevents the height and width of the potential barrier from being controlled by the static induction effect. Consequently, conventional transistors such as npn-type bipolar transistors have room to be improved for operation at higher speeds.
Fabrication of semiconductor devices such as semiconductor memories has to rely on crystal growth processes with film thickness controllability for controlling film thicknesses in units of molecular layers of semiconductor crystals and also with positional controllability. Specifically, low-temperature growth and low-temperature fabrication processes are required because a semiconductor device has to be fabricated based on sharp control of an impurity distribution and a crystal composition in units of a single molecular layer of crystals.
Crystal growth processes which meet the above requirements include a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and a molecular layer epitaxy (MLE) process.
The MBE process, which is essentially an evaporation process, does not ensure molecular layer growth in principle in its growth process though it can control a film thickness in units of a single molecular layer. In order to produce a crystal of good quality with the MBE process, the growth temperature of the conventional MBE process is about 200.degree. C. higher than that of the MLE process. Because the Debye temperature of gallium arsenide (GaAs) is of about 360K in a temperature range of 140K or higher, the process temperature difference of 200.degree. C. is highly conducive to the generation of defects in the device. It is difficult for the MOCVD process, which employs a metal organic gas, to produce highly thin layers of good quality successively in reality in view of the requirements for appropriate low process temperatures and film thickness/composition controllability in units of a single molecular layer.
Among the above three processes, the MLE process is most suitable for meeting the above requirements as it allow a crystal to grow one molecular layer by one molecular layer at low temperatures. To form a metal electrode after a semiconductor crystal of one molecular layer has grown, the semiconductor crystal is taken out of an MLE chamber and then surface-treated, and thereafter a metal electrode is formed on the semiconductor crystal by evaporation. Since the MLE process includes a step where the semiconductor crystal is exposed to air, an oxide layer grows on the surface of the semiconductor crystal. Therefore, the MLE process needs an improvement with respect to the formation of a metal-to-semiconductor contact of good quality.